1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a Si metal oxide semiconductor field effect transistor (MO SFET), and to a method of forming metal silicide contacts to a Si MOSFET.
2. Description of the Related Art
Self-aligned silicide (salicide) is an integral process in the fabrication of high-speed complementary metal oxide semiconductor (CMOS) devices. The salicide process converts the surface portions of the source, drain, and gate silicon regions into a silicide.
FIG. 1 illustrates a structure 100 having a source 101, a drain 102, a gate 103, and a silicided portion 104 of the drain. In FIG. 1, Xj is the source or drain junction depth, Xsil is the silicide junction depth and Rp is the peak dopant concentration.
Due to the low sheet resistance of the silicide film, the series resistance to the intrinsic device is minimized. The silicide film must be contained within the source and drain junction or otherwise it would form a leakage path to the substrate. Moreover, to obtain a good ohmic contact, it is desirable to target the silicide/silicon junction to coincide with the peak concentration of the source/drain doping. These requirements are illustrated in FIG. 1. Specially, Xj must be greater than Xsil, and Xsil roughly equals Rp.
That is, scaling the gate length of a MOSFET requires shallow junctions to suppress short channel effects (SCE). The junction depth is expected to become comparable or even thinner than the silicide film thickness. Meeting the shallow junction requirement and maintaining a thick enough silicide film require a revision of the conventional salicide process.
Scaling of the silicon-on-insulator (SOI) MOSFET leads to similar constraints on the salicide process. In the case of SOI, reducing the channel thickness (tsi) was found to have an important role in suppressing SCE for both single-gate and double-gate MOSFETs (e.g., see H-S. P. Wong et al., Int. Electron Device Meeting (IEDM), p. 407, (1998)).
The use of the conventional salicide process with devices having a very thin SOI channel leads to the following problems.
That is, there may not be enough silicon in the source and drain regions to complete the silicide formation. Furthermore, even a consumption of more than 80% of the silicon film would actually increase the series resistance due to a reduction in the contact area (e.g., see Lisa T. Su et al., Electron Device Letters, 15(9), p. 363, (1994)). Constraints on the silicon consumption by silicide imposed by future bulk and SOI technologies require altering the conventional salicide process to be compatible with ultra-shallow junction technology and ultra-thin SOI films.
Adding silicon selectively to the source, drain, and gate prior to the formation of the silicide film would allow the use of the conventional silicide process with shallow junctions and thin SOI devices. Such thickening of the source and drain may be achieved by selective epitaxy, a process that adds silicon only to the source, drain, and gate regions.
FIG. 2 illustrates a MOSFET structure having a silicon substrate 1, a shallow junction 2, a gate dielectric 3 formed under the gate 4, with a thickened silicon source and drain 6 formed by epitaxy. The Si epitaxy must be selective. Otherwise, silicon will be deposited on the device sidewalls 5 (e.g., gate spacers) which would short the source and drain to the gate 4.
However, selective silicon epitaxy usually requires relatively high growth temperatures, which may lead to dopant redistribution and dopant deactivation. Moreover, since the growth is selective, the process is very sensitive to surface preparation, thereby making it a difficult technique for production. For example, the existence of even a mono-layer of oxide would prohibit the silicon growth.
In view of the problems discussed above and other problems, disadvantages, and drawbacks of the conventional methods, an object of the present invention is to provide a self-aligned (salicide) method which is applicable to devices having shallow junctions and/or thin SOI films.
It is noted that, for the sake of simplicity, the method (and structure) discussed herein is for the specific case of Cobalt (Co) silicide. Although Co silicide may be of special interest due to its superior properties, the method is general and applicable to silicides formed with other metals such as Ti, Pt, Ni, Pd, W, etc.
In a first aspect of the invention, a method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
It is noted that there are two variants of the method. One variant is applicable to shallow Ge implants which amorphize only a very thin portion of the Si surface. The second variant relates to the case where the Ge implant is deeper. The first case does not require a re-crystallization anneal after the Ge implant, since the amorphized film formed by the implant is entirely consumed by monosilicide formation. The second case requires adding an anneal step after the Ge implant and prior to forming the blanket metal-silicon mixture layer.
In a second aspect of the invention, a method (and structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of the silicon-containing region, includes implanting Ge into the silicon-containing region, implanting a dopant into the silicon containing region, annealing the silicon-containing region to activate dopants, forming a blanket metal-silicon mixture layer over the silicon containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
The above-mentioned second aspect demonstrates that the Ge implant, for controlling the silicide formation, can be combined with the Ge implants routinely performed prior to the dopant implants, even though the Ge implant for silicide formation control requires about ten times the implant dose of that used conventionally before dopant implant. Further, the re-crystallization anneal can be combined with the routinely used dopant activation anneal, even though for re-crystallization a lower temperature anneal (by about 100C) is needed.
In a third aspect of the invention, a method (and structure) of forming a semiconductor structure, includes providing a semiconductor substrate to be silicided including a source region and a drain region formed on respective sides of a gate, implanting Ge into the source, drain and gate regions, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon film with Si at a first temperature to form a metal-silicon alloy, etching unreacted portions of the metal-silicon mixture, forming a silicon film over the metal-silicon alloy, annealing the structure at a second temperature to form a metal-Si2 alloy, and selectively etching the unreacted Si.
In a fourth aspect of the invention, a method (and structure) for forming a metal silicide contact on a silicon-germanium-containing region at a low formation temperature, includes amorphizing the silicon-germanium-containing region, forming a blanket metal-silicon mixture layer over the silicon-germanium-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.
With the unique and unobvious method and structure of the invention, a new self-aligned silicide process (and resulting structure) for shallow junction and/or thin SOI source and drain contacts is provided. The inventive process reduces the Si consumption from the source and drain, and thus allows silicide formation over shallow junction and on thin SOI films.
The inventive process is also compatible with single-gate and double-gate MOSFET structures having non-planar source and drain, and in addition, by amorphizing a SiGe alloy, the silicide formation temperature in the alloy can be lowered to that of pure Si. Thus, the invention uses Ge implants to control the temperature of the silicide formation.